1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layers.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the “two year/half-size rule” (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.18 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constants of less than 4.0) to reduce the capacitive coupling between adjacent metal lines. One such low k material comprises silicon, oxygen, and carbon, and may be deposited as a dielectric material in fabricating damascene features. One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form vertical interconnects, i.e., vias, and horizontal interconnects, i.e., trenches or lines, of a feature definition. Conductive materials, such as copper and barrier layer materials used to prevent diffusion of copper into the surrounding low k dielectric are then inlaid into the etched pattern. Any excess copper and barrier layer materials external to the etched pattern, such as on the field of the substrate, are then removed.
However, forming damascene structures require the use of lithographic processes. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers on a substrate. Many of these underlying material layers are reflective to ultraviolet light. Such reflections can distort the dimensions of features definitions, such as trenches and vias that are formed in the energy sensitive resist material. One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist.
However, conventional ARC materials as well as barrier materials and etch stops, may contain nitrogen, for example, silicon nitrides and metal nitrides may be used as ARC materials, barrier materials, and/or etch stops. The presence of nitrogen may chemically alter the composition of the photoresist material. The chemical reaction between nitrogen and the photoresist material is referred to as photoresist poisoning. The altered photoresist material may not be lithographically patterned as expected and result in imprecisely formed features in the photoresist material or excessive photoresist residue remaining on the substrate surface after photoresist patterning, both of which can detrimentally affect subsequent processes, such as etching processes. For example, nitrogen may neutralize acid near a photoresist and ARC interface and result in residue formation, known as footing, which can further result in curved or rounded aspects at the interface of the bottoms and sidewalls of features rather than desired right angles.
Nitrogen may originate directly from deposited materials adjacent the resist layer and may also contaminate the resist material indirectly, such as by diffusion through one or more layers, outgassing of materials during processing steps, such as annealing and plasma treatment, and by etching processes which may expose underlying nitrogen containing layers, such as silicon nitride etch stops, to any subsequently deposited resist materials. Other materials that may also produce resist poisoning, including basic materials such as hydroxyl groups, may be exposed to the photoresist material by the same processes that can result in nitrogen exposure.
Therefore, there remains a need for an improved process and material for depositing and patterning dielectric materials with minimal resist poisoning for damascene applications.